// ****************************************************************************** 
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  stars_pciedma_s_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2020/04/01
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2021/10/23 09:27:29 Create file
// ******************************************************************************

#ifndef __STARS_PCIEDMA_S_REG_REG_OFFSET_FIELD_H__
#define __STARS_PCIEDMA_S_REG_REG_OFFSET_FIELD_H__

#define STARS_PCIEDMA_S_REG_CFG_POOL_SEC_LEN    1
#define STARS_PCIEDMA_S_REG_CFG_POOL_SEC_OFFSET 0

#define STARS_PCIEDMA_S_REG_PCIEDMA_AWSNOOP_LEN    1
#define STARS_PCIEDMA_S_REG_PCIEDMA_AWSNOOP_OFFSET 5
#define STARS_PCIEDMA_S_REG_PCIEDMA_AWCACHE_LEN    4
#define STARS_PCIEDMA_S_REG_PCIEDMA_AWCACHE_OFFSET 1

#define STARS_PCIEDMA_S_REG_PCIEDMA_AWPROT_S_LEN    3
#define STARS_PCIEDMA_S_REG_PCIEDMA_AWPROT_S_OFFSET 0

#define STARS_PCIEDMA_S_REG_PCIEDMA_AWPROT_NS_LEN    3
#define STARS_PCIEDMA_S_REG_PCIEDMA_AWPROT_NS_OFFSET 0

#define STARS_PCIEDMA_S_REG_PCIEDMA_ENABLE_CTRL_S_LEN    8
#define STARS_PCIEDMA_S_REG_PCIEDMA_ENABLE_CTRL_S_OFFSET 0

#define STARS_PCIEDMA_S_REG_PCIEDMA_DISABLE_CTRL_S_LEN    8
#define STARS_PCIEDMA_S_REG_PCIEDMA_DISABLE_CTRL_S_OFFSET 0

#define STARS_PCIEDMA_S_REG_PCIEDMA_ENABLED_STATUS0_S_LEN    8
#define STARS_PCIEDMA_S_REG_PCIEDMA_ENABLED_STATUS0_S_OFFSET 0

#define STARS_PCIEDMA_S_REG_PCIEDMA_BASE_ADDR_LOW_LEN    32
#define STARS_PCIEDMA_S_REG_PCIEDMA_BASE_ADDR_LOW_OFFSET 0

#define STARS_PCIEDMA_S_REG_PCIEDMA_BASE_ADDR_IS_VIRTUAL_LEN    1
#define STARS_PCIEDMA_S_REG_PCIEDMA_BASE_ADDR_IS_VIRTUAL_OFFSET 31
#define STARS_PCIEDMA_S_REG_PCIEDMA_BASE_ADDR_SHIFT_LEN         5
#define STARS_PCIEDMA_S_REG_PCIEDMA_BASE_ADDR_SHIFT_OFFSET      17
#define STARS_PCIEDMA_S_REG_PCIEDMA_BASE_ADDR_HIGH_LEN          17
#define STARS_PCIEDMA_S_REG_PCIEDMA_BASE_ADDR_HIGH_OFFSET       0

#endif // __STARS_PCIEDMA_S_REG_REG_OFFSET_FIELD_H__
